Historically, digital devices have used detection of high voltage levels (typically 12-15 volts) on a particular input-output (I/O) pin to enable test or programming modes. However, in read only memory (ROM) and smaller geometry flash memory processes, there may not be circuits capable of detecting nor withstanding these high voltages. Typically, specific logic levels defining the testing and/or programming modes are coupled to a number of parallel input-output (I/O) pins of an integrated circuit digital device having a large number of I/O pins available. However for I/O pin constrained digital devices this is not practical or even possible.